Resistor Random Access Memory Structure Having a Defined Small Area of Electrical Contact

ABSTRACT

A memory cell device, of the type that includes a memory material switchable between electrical property states by application of energy, includes first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed. Also, methods for making the device include steps of constructing a dielectric form over a first electrode, and forming a conductive film over the dielectric form.

BACKGROUND

1. Field of the Invention

This invention relates to high density memory devices based on phase change based memory materials, including chalcogenide based materials and other materials, and to methods for manufacturing such devices.

2. Description of Related Art

Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change.

Phase change based memory materials, such as chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access.

The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. It is desirable to minimize the magnitude of the reset current used to cause transition of phase change material from crystalline state to amorphous state. The magnitude of the reset current needed for reset can be reduced by reducing the size of the phase change material element in the cell and by reducing the size of the contact area between electrodes and the phase change material, so that higher current densities are achieved with small absolute current values through the phase change material element.

One direction of development has been toward forming small pores in an integrated circuit structure, and using small quantities of programmable resistive material to fill the small pores. Patents illustrating development toward small pores include: Ovshinsky, “Multibit Single Cell Memory Element Having Tapered Contact,” U.S. Pat. No. 5,687,112, issued Nov. 11, 1997; Zahorik et al., “Method of Making Chalogenide [sic] Memory Device,” U.S. Pat. No. 5,789,277, issued Aug. 4, 1998; Doan et al., “Controllable Ovonic Phase-Change Semiconductor Memory Device and Methods of Fabricating the Same,” U.S. Pat. No. 6,150,253, issued Nov. 21, 2000.

Problems have arisen in manufacturing such devices with very small dimensions, and with variations in process that meet tight specifications needed for large-scale memory devices. It is desirable therefore to provide a memory cell structure having small dimensions and low reset currents, and a method for manufacturing such structure.

SUMMARY

Generally, the invention features a memory cell device of the type that includes a memory material switchable between electrical property states by application of energy. The memory cell device has first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug. The dielectric form is wider near the first electrode, and is narrower near the phase change plug. The area of contact of the conductive film with the phase change plug is defined in part by the geometry of the dielectric form over which the conductive film is formed.

In one general aspect the invention features a memory cell device including first and second electrodes, a plug of memory material (such as phase change material) which is in electrical contact with the second electrode, and an electrically conductive film which is supported by a dielectric form and which is in electrical contact with the first electrode and with the memory material plug.

In various embodiments the dielectric form is wider near the first electrode, and is narrower near the phase change plug, the dielectric form may be shaped as a cone (with a generally circular or elliptical base); a pyramid (with a generally rectangular or square base); a wedge (with an elongated generally rectangular base); or a truncated cone or pyramid or wedge. Where the form is truncated the area of contact of the conductive film with the phase change plug is defined in part by the area of the truncation, which may be controlled for precision and accuracy by the process of shaping the dielectric form.

The electrically conductive film contacts edge portions of the first electrode. Accordingly, the conductive film is a shell, and the shape of the conductive film is defined in part by the shape of the dielectric form and in part by the edge portions of the first electrode.

In another general aspect the invention features a method for making a memory cell device, by: providing a substrate having an intermetal dielectric at a surface; forming a first electrode layer over the intermetal dielectric, and patterning the first electrode layer to form first (bottom) electrodes; depositing a first dielectric material over the substrate and the bottom electrodes; removing a portion of the first dielectric material to expose edge portions of the bottom electrodes and to leave shaped dielectric forms on the bottom electrodes and a first dielectric layer between the bottom electrodes; forming a film of an electrically conductive material over the dielectric forms and the exposed edges of the bottom electrodes; forming a cap film over the electrically conductive film; patterning the cap film and the electrically conductive film to isolate conductive films and cap films over individual electrodes; depositing a second dielectric material over the cap films and the first dielectric layer; removing a portion of the second dielectric material to expose portions of the cap films; removing exposed portions of the cap films to expose areas of the electrically conductive films; depositing a phase change material over the exposed areas of the electrically conductive films and the second dielectric layer; depositing a second electrode layer over the phase change material layer; and patterning the second electrode layer and the phase change material layer to form isolated phase change plugs in contact with the exposed areas of the electrically conductive films and second electrodes.

The various steps in the method may be carried out in any of a variety of processes, of which a few examples follow. The substrate may be provided as a wafer having a layer of oxide on a semiconductor such as silicon or gallium arsenide, or having a back end of line (BEOL) layer. The dielectric material may be deposited in a high density plasma (HDP) process, which may be a chemical vapor deposition process (HDP-CVD) or a fluorinated silica glass process (HDP-FSG), or a phosphosilicate glass process (HDP-PSG), or a silicon nitride process (HDP-SIN), or a boron-doped phosphosilicate glass process (HDP-BPSG). The first dielectric material may be removed by a selective etch process such as a selective wet etch or a selective dry etch. The film of electrically conductive material may be formed by sputtering, such as by DC sputtering; for a TiN material a gas mixture of Ar and N₂ may be flowed through the chamber, and a Ti target may be employed. The cap film may be formed as a film of a material having a higher CMP selectivity as compared with the second dielectric material to be deposited subsequently. The second dielectric material may be deposited as an oxide, or as a fluorinated silica glass (FSG) or as a low-K dielectric (having a lower dielectric constant than silicon dioxide, for example). The cap film may be formed in a vapor deposition process; for a SiN cap film a gas mixture of SiH₄ and N₂ may be flowed through the chamber under conditions of controlled pressure and RF power. The cap film and electrically conductive film may be patterned in a mask and etch process. The removal of a portion of the second dielectric material may be by a CMP process, such as material selective CMP process; where the electrically conductive material is TiN and the second dielectric material is silicon dioxide, for example, the CMP process may employ a CeO₂ slurry. Or, the removal of a portion of the second dielectric material may be by a CMP process, followed by an etch where the electrically conductive material is TiN and the second dielectric material is silicon dioxide, for example, the CMP process may employ a CeO₂ slurry, and the etch may be a HF etch.

In at least some embodiments the shape and the size of the area of contact of the phase change plug and the conductive film is determined at least in part by the shape and dimensions of the dielectric form upon which the conductive film is formed; and in at least some embodiments the shape and the size of the area of contact of the phase change plug and the conductive film is determined at least in part by the shape and dimensions of the exposed surface of the cap film,

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a diagrammatic sketch in a sectional view showing two adjacent memory cell devices according to an embodiment of the invention.

FIG. 1B is a diagrammatic sketch in a sectional view showing one of the memory cell devices as in FIG. 1A, enlarged.

FIG. 2A is a diagrammatic sketch in a sectional view showing two adjacent memory cell devices according to another embodiment of the invention.

FIG. 2B is a diagrammatic sketch in a sectional view showing one of the memory cell devices as in FIG. 2A, enlarged.

FIG. 3 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following deposition and patterning of bottom electrodes.

FIG. 4 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following deposition of dielectric over the bottom electrodes and the substrate formed as shown in FIG. 3.

FIG. 5 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following wet etch of the dielectric layer formed as shown in FIG. 4, to expose shoulders of the bottom electrode.

FIG. 6 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following deposition of a conductive film and a cap film over a structure as shown in FIG. 5.

FIG. 7 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following patterning of the conductive film and the cap film formed as shown in FIG. 6.

FIG. 8 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following deposition of a dielectric over the structure as shown in FIG. 7 and planarization of the dielectric layer to expose small portions of the cap film.

FIG. 9 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following removal of exposed portions of the cap layer of the structure as shown in FIG. 8, to expose small areas of the conductive film.

FIG. 10 is a diagrammatic sketch in a sectional view showing a stage in a process for constructing a device according to an embodiment of the invention, following deposition of a phase change material layer and a top electrode material layer over a structure as in FIG. 9, and patterning to form phase change plugs and top electrodes.

FIGS. 11-18 are diagrammatic sketches in a sectional view showing stages in a process for constructing a device according to another embodiment of the invention.

FIG. 19 is a schematic diagram for a memory array comprising phase change memory elements.

DETAILED DESCRIPTION

The invention will now be described in further detail by reference to the drawings, which illustrate alternative embodiments of the invention. The drawings are diagrammatic, showing features of the invention and their relation to other features and structures, and are not made to scale. For improved clarity of presentation, in the FIGS. illustrating embodiments of the invention, elements corresponding to elements shown in other drawings are not all particularly renumbered, although they are all readily identifiable in all the FIGS.

Turning now to FIGS. 1A, 1B, there is shown a phase change memory cell 10 according to an embodiment of the invention. The memory cell includes a bottom electrode 144, an electrically conductive film 102, a cap film 104, a phase change material plug 112, and a top electrode 114. The electrically conductive film is supported by a dielectric form 64, which is wider at the bottom, where it rests upon the bottom electrode, and is narrower at the top. Various shapes for the dielectric form are contemplated, including for example: a cone (with a generally circular or elliptical base); a pyramid (with a generally rectangular or square base); a wedge (with an elongated generally rectangular base); or, in embodiments as in FIGS. 1A, 1B, a truncated cone or pyramid or wedge. The electrically conductive film 102 contacts edge portions 68 of the bottom electrode 144. Accordingly, the conductive film is a shell, and the shape of the conductive film is defined in part by the shape of the dielectric form and in part by the edge portions of the bottom electrode. An opening through the cap film 104 exposes a small limited area 106 of the surface of the conductive film 102 at the top, and the phase change plug 112 makes contact with the conductive film at this limited area. The top electrode 114 contacts the top surface of the phase change plug 112. Current flows through the cell as indicated generally by the arrow 12; more particularly, the current flows from the top electrode through the phase change plug, to the conductive film across the limited area defined by the opening through the cap film, and through the conductive film to the bottom electrode by way of contact of the conductive film with the edge portions of the bottom electrode.

Referring now to FIGS. 2A, 2B, there is shown a phase change memory cell 20 according to another embodiment of the invention. The memory cell includes a bottom electrode 244, an electrically conductive film 202, a cap film 204, a phase change material plug 212, and a top electrode 214. The electrically conductive film is supported by a dielectric form 264, which is wider at the bottom, where it rests upon the bottom electrode, and is narrower at the top. The dielectric form contemplated in embodiments as in FIGS. 2A, 2B is not truncated (as they are in embodiments as in FIGS. 1A, 1B), and the various shapes including for example: a cone (with a generally circular or elliptical base); a pyramid (with a generally rectangular or square base); or a wedge (with an elongated generally rectangular base). The electrically conductive film 202 contacts edge portions 268 of the bottom electrode 244. Accordingly, the conductive film is a shell, and the shape of the conductive film is defined in part by the shape of the dielectric form and in part by the edge portions of the bottom electrode. An opening through the cap film 204 exposes a small limited area 206 of the surface of the conductive film 202 at the top, or apex, and the phase change plug 212 makes contact with the conductive film at this limited area. The top electrode 214 contacts the top surface of the phase change plug 212. Current flows through the cell as indicated generally by the arrow 22; more particularly, the current flows from the top electrode through the phase change plug, to the conductive film across the limited area defined by the opening through the cap film, and through the conductive film to the bottom electrode by way of contact of the conductive film with the edge portions of the bottom electrode.

Embodiments of the memory cell include phase change based memory materials, including chalcogenide based materials and other materials, for the memory material (112. 212). Phase change alloys are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These alloys are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states. The electrical properties in the material may vary accordingly.

Phase change alloys can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined, without undue experimentation, specifically adapted to a particular phase change alloy. In the disclosure herein, the phase change material is referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory device described herein is Ge₂Sb₂Te₅.

With reference again to FIGS. 1A, 1B, or 2A, 2B, access circuitry can be implemented to contact the first electrode 144 (244) and the second electrode 114 (214) in a variety of configurations for controlling the operation of the memory cell, so that it can be programmed to set the phase change material 112 (212) in one of the two solid phases that can be reversibly implemented using the memory material. For example, using a chalcogenide-based phase change memory material, the memory cell may be set to a relatively high resistivity state in which at least a portion of the bridge in the current path is an amorphous state, and a relatively low resistivity state in which most of the bridge in the current path is in a crystalline state. For example, application of an electrical pulse having a suitable shorter, high amplitude profile, for example, results in changing the phase change material 112 (212) locally to a generally amorphous state, as indicated at 116 in FIG. 1B (216 in FIG. 2B).

A memory cell structure according to an embodiment of the invention as shown for example in FIGS. 1A and 1B (or, similarly, in FIGS. 2A and 2B) can be constructed as shown with reference to FIGS. 3 through 10. Referring now to FIG. 3, a layer of an electrically conductive material suitable as a bottom electrode is deposited upon a dielectric substrate 32 and patterned, for example by masking and etching, to form bottom electrodes 34. Suitable substrates include, for example, an oxide on silicon or gallium arsenide; or a back end of line (BEOL) layer, as in a PCRAM construct.

Then a layer of a dielectric material, such as for example a silicon dioxide, is formed over the substrate, covering the patterned bottom electrodes, as shown in FIG. 4. The dielectric material covers the substrate 32 as shown at 42 in FIG. 4 and also covers the patterned bottom electrodes 34 as shown at 44 in FIG. 4. The dielectric material layer may be formed, for example, by high density plasma chemical vapor depositions (HDP-CVD). The layer may have a thickness in the range about 500 A to 2000 A, such as about 1000 A. The layer may be formed, for example, by a high density plasma (HDP) process, and may include HDP fluorinated silica glass (HDP FSG), or HDP phosphosilicate glass (HDP PSG), or HDP SIN, or HDP boron-doped phosphosilicate glass (HDP BPSG), for example.

Then a portion of the dielectric layer is removed, as shown in FIG. 5, to expose edge portions 58 of the bottom electrodes, as indicated by the circles 57. A remaining portion 52 of the dielectric layer 42 covers the substrate adjacent the patterned electrodes 34, and a portion of the dielectric layer remains over each patterned electrode 34, constituting a form 54 upon which the electrically conductive film is to be formed. The material may be removed by, for example, a wet etch using a high etch selectivity ratio between the dielectric layer 42, 44 material and the bottom electrode 34 material. The materials should be selected accordingly; for example, if the dielectric layer material is silicon dioxide, then the bottom electrode material can be, for example, TaN or TiN. The electrode material is selected for compatibility with the programmable resistive memory material, and to act as a diffusion barrier between the conductive material and a phase change material. Alternatively, the electrode material may be TiAIN or TaAIN, or may comprise, as further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof.

Then a film of an electrically conductive material is formed over the structure shown in FIG. 5, as illustrated at 62 in FIG. 6. The conductive film 62 covers the surface of the dielectric layer 52 over the substrate 32, the forms 54, and the edge portions 58 of the bottom electrodes 34. Suitable materials for the conductive film include, for example, TiN and TaN. The electrode material is selected for compatibility with the programmable resistive memory material, and to act as a diffusion barrier between the conductive material and a phase change material. Alternatively, the electrode material may be TiAIN or TaAIN, or may comprise, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof. The electrically conductive film 62 has a thickness in the range about 22 angstroms to about 500 angstroms, usually about 50 angstroms.

Suitable methods for forming the electrically conductive film include, for example, sputtering. For deposition of TiN, for example, DC sputtering can be carried out using a gas mixture of Ar and N₂ and a Ti target. Deposition time will depend upon DC power level, for example about 4 sec at 6500 W power, and a longer duration at lower power, such as 1500 W. Then a cap film is formed over the electrically conductive film 62, as illustrated at 64 in FIG. 6. Suitable materials for the cap film include, for example, SiN. Other cap film materials may be employed; the cap film 64 should be of a material having a higher CMP selectivity to the material of the dielectric layer 82 to be formed subsequently (see FIG. 8), and SiN may be preferred for the cap film. Layer 82 could be an oxide, a fluorine-doped silica glass (FSG), or lower K dielectric, for example. Selectivity to oxide>50 can readily be obtained, using a CeO₂ slurry as the CMP slurry, for example; that is, under such circumstances treatment sufficient to remove 500 angstroms removes only about 10 angstroms from the SiN layer. The dielectric layer could replace SiN if higher CMP selectivity to dielectric layer 82. The cap film 64 has a thickness in the range about 100 angstroms to about 1000 angstroms, for example about 200 angstroms. Suitable methods for forming the cap film include, for SiN for example, deposition under the following conditions: SiH₄, about 195 sccm; N₂, about 8000 sccm; RF power, about 300 W; pressure, about 2.6 torr. The thickness of the resulting film can be controlled by controlling the deposition time.

Then the electrically conductive film and the cap film are patterned, for example in a mask-and-etch process, to isolate the conductive films 72 and cap films 74 over individual electrodes, as shown in FIG. 7. This exposes areas 76 of the surface of the dielectric layer 52. As illustrated in FIG. 7, the films are shells whose shapes are determined in part by the forms 54. Particularly, the shells 72, 74 are wide at the bottom where the conductive shell 72 contacts edge portions of the bottom electrode, and narrow at the top, where the cap shell 74 has a small area 78 at the top, where the shells are formed over the truncation at the top of the form 54.

Then a second dielectric layer is formed over the isolated films and the exposed surfaces of the dielectric layer, and a portion of the second dielectric layer is removed to expose the small areas 84 at the top of the cap film shells 74, and leaving portions 82 of the second dielectric layer, as illustrated in FIG. 8. The materials may be removed by, for example, either of various processes. In a first process, the upper portion of the second dielectric layer is removed by chemical mechanical polishing (CMP) to planarize the layer down to the small areas 84. It may be important to limit the extent of planarization in order to control the size of the exposed areas 84 of the cap film, and to control thereby the contact area of the phase change material with the electrically conductive film (see FIGS. 9 and 10). Generally, removal of the layer 82 should be stopped at the point where the top of the cap film is exposed, or in any event before a significant amount of the cap film material has been removed, and preferably before the top surface 106 of the conductive film is exposed; this may be accomplished during CMP, for example, by end point detection. Or, a material selective CMP can be applied. For example, where the dielectric material is a silicon dioxide and the cap film material is SiN, a CeO₂ slurry can be employed, as it provides a higher selectivity (Oxide:SiN>50:1). The polish can be stopped on a small area 84.

Alternatively, for example, a two-step process can be employed, including a CeO₂ slurry in a CMP planarization, followed by a HF dip to expose a small area of the cap film.

Then the exposed small areas 84 of the cap material are removed to form openings in the cap shell 74, as shown at W in FIG. 9, exposing a small area of the electrically conductive layer 72, leaving an electrically conductive shell 102 having a defined small area 106 exposed as shown in FIG. 9. The cap material can be removed, for example, by etch, selective to the material of the cap film material.

Then a layer of a phase change material is deposited over the structure shown in FIG. 9, and a layer of an electrically conductive material suitable as a top electrode is formed over the phase change material layer; and the layers are patterned to form phase change plugs 112 overlain by top electrodes 114, as shown for example in FIG. 10.

The process is controlled to define the width of the area 106 to within a range, for example, about 100 angstroms and about 500 angstroms. The shape of the forms 64 (and the dimensions of the can be readily controlled to good precision and accuracy by controlling the HDP deposition.

A memory cell structure according to an embodiment of the invention as shown for example in FIGS. 2A and 2B can be constructed as shown with reference to FIGS. 11 through 18. Referring now to FIG. 11, a layer of an electrically conductive material suitable as a bottom electrode is deposited upon a dielectric substrate 32 and patterned, for example by masking and etching, to form bottom electrodes 34. Suitable substrates include, for example, an oxide on silicon or gallium arsenide; or a BEOL layer, as in a PCRAM construct.

Then a layer of a dielectric material, such as for example a silicon dioxide, is formed over the substrate, covering the patterned bottom electrodes, as shown in FIG. 12. The dielectric material covers the substrate 32 as shown at 42 in FIG. 12 and also covers the patterned bottom electrodes 34 as shown at 44 in FIG. 4. The dielectric material layer may be formed, for example, by high density plasma chemical vapor depositions (HDP-CVD). The layer may have a thickness in the range about 500 A to 2000 A, such as about 1000 A. The layer may be formed, for example, by a high density plasma (HDP) process, and may include HDP fluorinated silica glass (HDP FSG), or HDP phosphosilicate glass (HDP PSG), or HDP SIN, or HDP boron-doped phosphosilicate glass (HDP BPSG), for example.

Then a portion of the dielectric layer is removed, as shown in FIG. 13, to expose edge portions 158 of the bottom electrodes, as indicated by the circles 157. A remaining portion 152 of the dielectric layer 42 covers the substrate adjacent the patterned electrodes 34, and a portion of the dielectric layer remains over each patterned electrode 34, constituting a form 154 upon which the electrically conductive film is to be formed. The material may be removed by, for example, a wet etch using a high etch selectivity ratio between the dielectric layer 42, 44 material and the bottom electrode 34 material. The materials should be selected accordingly; for example, if the dielectric layer material is silicon dioxide, then the bottom electrode material can be, for example, TaN or TiN. The electrode material is selected for compatibility with the programmable resistive memory material, and to act as a diffusion barrier between the conductive material and a phase change material. Alternatively, the electrode material may be TiAIN or TaAIN, or may comprise, as further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof.

Then a film of an electrically conductive material is formed over the structure shown in FIG. 13, as illustrated at 162 in FIG. 14. The conductive film 162 covers the surface of the dielectric layer 152 over the substrate 32, the forms 154, and the edge portions 158 of the bottom electrodes 34. Suitable materials for the conductive film include, for example, TiN and TaN. The electrode material is selected for compatibility with the programmable resistive memory material, and to act as a diffusion barrier between the conductive material and a phase change material. Alternatively, the electrode material may be TiAIN or TaAIN, or may comprise, for further examples, one or more elements selected from the group consisting of Ti, W, Mo, Al, Ta, Cu, Pt, Ir, La, Ni, and Ru and alloys thereof. The electrically conductive film 162 has a thickness in the range about 22 angstroms to about 500 angstroms, usually about 50 angstroms. Then a cap film is formed over the electrically conductive film 162, as illustrated at 164 in FIG. 14. Suitable materials for the cap film include, for example, SiN. Other cap film materials may be employed; the cap film 164 should be of a material having a higher CMP selectivity to the material of the dielectric layer 182 to be formed subsequently (see FIG. 16), and SiN may be preferred for the cap film, as described above. Of course, the dielectric layer could replace SiN if higher CMP selectivity to dielectric layer 182. The cap film 164 has a thickness in the range about 100 angstroms to about 1000 angstroms, for example about 200 angstroms. Suitable methods for forming the cap film include, for example, deposition, as described above.

Then the electrically conductive film and the cap film are patterned, for example in a mask-and-etch process, to isolate the conductive films 172 and cap films 174 over individual electrodes, as shown in FIG. 15. This exposes areas 176 of the surface of the dielectric layer 162. As illustrated in FIG. 15, the films are shells whose shapes are determined in part by the forms 154. Particularly, the shells 172, 174 are wide at the bottom where the conductive shell 172 contacts edge portions of the bottom electrode, and narrow at the top, where the cap shell 174 has a small area 178 at the top, where the shells are formed over the apex of the form 54.

Then a second dielectric layer is formed over the isolated films and the exposed surfaces of the dielectric layer, and a portion of the second dielectric layer is removed to expose small areas 184 at the top of the cap film shells 174, and leaving portions 182 of the second dielectric layer, as illustrated in FIG. 16. The materials may be removed by, for example, either of various processes. In a first process, the upper portion of the second dielectric layer is removed by chemical mechanical polishing (CMP) to planarize the layer down to the small areas 184. It may be important to limit the extent of planarization in order to control the size of the exposed areas 184 of the cap film, and to control thereby the contact area of the phase change material with the electrically conductive film (see FIGS. 17 and 18). Generally, removal of the layer 182 should be stopped at the point where a limited part of the top of the cap film is exposed, or in any event before a significant amount of the cap film material has been removed, and preferably before the top surface 206 of the conductive film is exposed; this may be accomplished during CMP, for example, by end point detection. Or, a material selective CMP can be applied. For example, where the dielectric material is a silicon dioxide and the cap film material is SiN, a CeO₂ slurry can be employed, as it provides a higher selectivity (Oxide:SiN >50:1). The polish can be stopped upon exposure of the small area 84.

Alternatively, for example, a two-step process can be employed, including a CeO₂ slurry in a CMP planarization, followed by a HF dip to expose a small area of the cap film.

Then the exposed small areas 184 of the cap material are removed to form openings in the cap shell 174, as shown at W′ in FIG. 17, exposing a small area of the electrically conductive layer 172, leaving an electrically conductive shell 202 having a defined small area 206 exposed as shown in FIG. 17. The cap material can be removed, for example, by etch, selective to the material of the cap film material.

Then a layer of a phase change material is deposited over the structure shown in FIG. 17, and a layer of an electrically conductive material suitable as a top electrode is formed over the phase change material layer; and the layers are patterned to form phase change plugs 212 overlain by top electrodes 214, as shown for example in FIG. 18.

FIG. 19 is a schematic illustration of a memory array, which can be implemented as described herein. In the schematic illustration of FIG. 19, a common source line 1928, a word line 1923 and a word line 1924 are arranged generally parallel in the Y-direction. Bit lines 1941 and 1942 are arranged generally parallel in the X-direction. Thus, a Y-decoder and a word line driver in block 1945 are coupled to the word lines 1923, 1924. An X-decoder and a set of sense amplifiers in block 1946 are coupled to the bit lines 1941 and 1942. The common source line 1928 is coupled to the source terminals of access transistors 1950, 1951, 1952 and 1953. The gate of access transistor 1950 is coupled to the word line 1923. The gate of access transistor 1951 is coupled to the word line 1924. The gate of access transistor 1952 is coupled to the word line 1923. The gate of access transistor 1953 is coupled to the word line 1924. The drain of access transistor 1950 is coupled to the bottom electrode member 1932 for memory cell 1935, which has top electrode member 1934. The top electrode member 1934 is coupled to the bit line 1941. Likewise, the drain of access transistor 1951 is coupled to the bottom electrode member 1933 for memory cell 1936, which has top electrode member 1937. The top electrode member 1937 is coupled to the bit line 1941. Access transistors 1952 and 1953 are coupled to corresponding memory cells as well on bit line 1942. It can be seen that in this illustrative configuration the common source line 1928 is shared by two rows of memory cells, where a row is arranged in the Y-direction in the illustrated schematic. In other embodiments, the access transistors can be replaced by diodes, or other structures for controlling current flow to selected devices in the array for reading and writing data.

Other embodiments are within the scope of the invention. 

1. A memory cell device, comprising first and second electrodes, a plug of memory material in electrical contact with the second electrode, and an electrically conductive film, the film being supported by a dielectric form and being in electrical contact with the first electrode and with the memory material plug.
 2. The memory cell device of claim 1 wherein the dielectric form is wider near the first electrode, and is narrower near the memory material plug.
 3. The memory cell device of claim 1 wherein the dielectric form is shaped as a cone having a generally circular or elliptical base.
 4. The memory cell device of claim 1 wherein the dielectric form is shaped as a pyramid having a generally rectangular or square base.
 5. The memory cell device of claim 1 wherein the dielectric form is shaped as a wedge having an elongated generally rectangular base.
 6. The memory cell device of claim 1 wherein the dielectric form is shaped as a truncated cone.
 7. The memory cell device of claim 1 wherein the dielectric form is shaped as pyramid.
 8. The memory cell device of claim 1 wherein the dielectric form is shaped as wedge.
 9. The memory cell device of claim 1 wherein the electrically conductive film contacts edge portions of the first electrode.
 10. A method for making a memory cell device, comprising: providing a substrate having an intermetal dielectric at a surface; forming a first electrode layer over the intermetal dielectric, and patterning the first electrode layer to form first electrodes; depositing a first dielectric material over the substrate and the bottom electrodes; removing a portion of the first dielectric material to expose edge portions of the bottom electrodes and to leave shaped dielectric forms on the bottom electrodes and a first dielectric layer between the bottom electrodes; forming a film of an electrically conductive material over the dielectric forms and the exposed edges of the bottom electrodes; forming a cap film over the electrically conductive film; patterning the cap film and the electrically conductive film to isolate conductive films and cap films over individual electrodes; depositing a second dielectric material over the cap films and the first dielectric layer; removing a portion of the second dielectric material to expose portions of the cap films; removing exposed portions of the cap films to expose areas of the electrically conductive films; depositing a phase change material over the exposed areas of the electrically conductive films and the second dielectric layer; depositing a second electrode layer over the phase change material layer; and patterning the second electrode layer and the phase change material layer to form isolated phase change plugs in contact with the exposed areas of the electrically conductive films and second electrodes.
 11. The method of claim 10 wherein providing a substrate comprises providing a wafer having a layer of oxide on a semiconductor.
 12. The method of claim 10 wherein providing a substrate comprises providing a wafer having a layer of oxide on silicon.
 13. The method of claim 10 wherein providing a substrate comprises providing a wafer having a layer of oxide on gallium arsenide.
 14. The method of claim 10 wherein providing a substrate comprises providing a wafer comprising a BEOL layer.
 15. The method of claim 10 wherein depositing a first dielectric material comprises an HDP-CVD process.
 16. The method of claim 10 wherein depositing a first dielectric material comprises an HDP-FSG process.
 17. The method of claim 10 wherein depositing a first dielectric material comprises an HDP-PSG process.
 18. The method of claim 10 wherein depositing a first dielectric material comprises an HDP-SIN process.
 19. The method of claim 10 wherein depositing a first dielectric material comprises an HDP-BPSG process.
 20. The method of claim 10 wherein removing a portion of the first dielectric material comprises a selective etch process.
 21. The method of claim 10 wherein the step of forming a film of electrically conductive material over the dielectric forms comprises sputtering.
 22. The method of claim 21 wherein the sputtering comprises DC sputtering.
 23. The method of claim 21 wherein the sputtering comprises DC sputtering using a gas mixture of Ar and N₂ and a Ti target, and the electrically conductive material comprises TiN.
 24. The method of claim 10 wherein forming a cap film comprises forming a film of a material having a higher CMP selectivity to the second dielectric material.
 25. The method of claim 10 wherein depositing a second dielectric material comprises depositing an oxide.
 26. The method of claim 10 wherein depositing a second dielectric material comprises depositing a FSG.
 27. The method of claim 10 wherein depositing a second dielectric material comprises depositing a low K dielectric.
 28. The method of claim 10 wherein forming a cap film comprises a vapor deposition process.
 29. The method of claim 10 wherein forming a cap film comprises vapor deposition using a flow of SiH₄ and N₂, and the cap film comprises SiN.
 30. The method of claim 10 wherein forming a cap film comprises vapor deposition using a flow of SiH₄ about 195 sccm and a flow of N₂ about 8000 sccm under about 2.6 torr pressure and at about 300 W RF power, and the cap film comprises SiN.
 31. The method of claim 10 wherein patterning the cap film and the electrically conductive film comprises a mask and etch process.
 32. The method of claim 10 wherein removing a portion of the second dielectric material comprises a CMP process.
 33. The method of claim 10 wherein removing a portion of the second dielectric material comprises a material selective CMP process.
 34. The method of claim 33 wherein forming a film of an electrically conductive material comprises forming a film of TiN and depositing a second dielectric material comprises depositing a silicon oxides and wherein removing a portion of the second dielectric material comprises a CMP process employing a CeO₂ slurry.
 35. The method of claim 10 wherein removing a portion of the second dielectric material comprises a CMP process followed by an etch.
 36. The method of claim 35 wherein removing a portion of the second dielectric material comprises a CMP process employing a CeO₂ slurry followed by an etch employing HF. 